IEEE/ANSI standard 1149.1 - 1990, also known as JTAG and Boundary Scan, is a standard for testing integrated circuits as well as circuit boards. In the prior art, printed circuit boards were tested by automatic test equipment (ATE) which contacted special locations on a board by means of probe wires attached to a probe card. The probe card interfaced with the ATE in a manner such that test signals could be sent to and from the ATE to specific areas of a board under test. On the other hand, Boundary Scan requires that certain registers and dedicated pins be placed on a chip so that software can be used to implement test procedures, rather than ATE. Relatively inexpensive computers can now be used to test integrated circuit chips even after the chip is manufactured and shipped. Five dedicated pins provided on chips with a Boundary Scan test capability communicate with a Test Access Port (TAP) which gives access to logic which executes Boundary Scan and other test procedures. The pins are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK), Test Mode Select (TMS) and Test Reset (TRST).
Three of the five dedicated pins, namely TMS, TCK and TRST, access a simple state machine, with 16 states, known as the TAP Controller. In turn, the TAP Controller, together with dedicated pins TDI and TDO communicate with an Instruction Register, as well as with two other registers which are mandatory in any Boundary Scan implementation. These are the Boundary Scan Register and the Bypass Register. The Instruction Register, in turn, communicates with other registers, known generally as Data Registers, some of which may be user-defined. The Data Registers allow for device configuration, verification, test, reliability evaluation and so on. One further important feature of Boundary Scan architecture is a set of test cells, one cell being associated with each of the functional input/output pins of the integrated circuit so that a cell may be used as an input or output cell for the device. The cells are arranged in a shift-register organization for serial communication between the TDI and TDO pins.
The JTAG standard has two major modes of operation, non-invasive mode and pin-permission mode. The standard specifies a set of circuitry guaranteed to be independent of the rest of the logic within an integrated circuit (IC). The logic circuitry within an IC excluding the JTAG circuitry is defined as the on-chip system logic (OCSL). In non-invasive mode, the JTAG circuitry is used to communicate asynchronously with the outside world to set up tests or to read out results. These activities do not affect the normal behavior of the IC. In pin-permission mode, the JTAG standard specifies instruction modes of operation that can take over control of input/output (I/O) pins of the IC, effectively disconnecting the OCSL from the outside world. These modes allow the testing of the OCSL or its isolation from testing activities taking place at its pins. Among the pin-permission instructions taught are INTEST, EXTEST and RUNBIST. The INTEST instruction allows the Boundary Scan Register to apply stimulus to and to capture test results from the OCSL of the device. The EXTEST instruction allows the Boundary Scan Register to apply stimulus to and capture test results from board level connections between integrated circuits. The RUNBIST instruction is similar to the INTEST instruction, except that it may target any designer specified register between pins TDI and TDO (which may or may not include the Boundary Scan Register).
After certain JTAG operations, the devices OCSL may need to be reset in order to return to normal operation. Among these operations are RUNBIST, INTEST, EXTEST, CLAMP and HIGHZ. An OCSL reset may also be required after executing design-specific, non-standard instructions.
In an integrated circuit using the JTAG test methodology, a device reset would normally be performed either by (1) asserting a TRST pin, which loads the BYPASS or IDCODE instruction into the Instruction Register, or (2) removing, then re-applying device power, or (3) removing a compliance-enable data pattern from a set of compliance-enable pins, or (4) traversing the Test Access Port controller to the Test-Logic-Reset state. Each of these actions sets the TAP controller to the Test-Logic-Reset state, and configures the test logic such that it does not affect OCSL operation. Each of these procedures also loads the Instruction Register with the BYPASS (or, if it exists, the IDCODE) instruction code.
The Instruction Register content may also be changed by traversing the TAP controller through the Update-IR state. In fact, this is the only method that the JTAG specification provides for changing the Instruction Register content to anything other than the BYPASS (or IDCODE) instruction. Therefore, this is the only method taught by which the instruction may be changed without configuring the test logic such that it does not affect OCSL operation.
Within the present JTAG test logic structure, there are operations where the OCSL's operation may need to be controlled such that the OCSL cannot be damaged. Among these operations are the execution of the EXTEST, CLAMP and HIGHZ instructions. The JTAG specification states that such control, if required, must occur while the specific instruction is selected. Also, other instructions may require different alterations to the OCSL's operation. For example, while the INTEST instruction is selected, the OCSL must be capable of a single step clocking operation (IEEE 1149.1a 7.8.1.c).
Table A shows the minimum set of instructions that must be included within an IC in order for the IC to be compliant with the JTAG specifications. Only the BYPASS, EXTEST and SAMPLE/PRELOAD instructions are required by the IEEE 1149.1 specification.
TABLE A ______________________________________ Minimum JTAG instruction set. PRIOR ART Instruction Name Register IR Code ______________________________________ Extest Boundary Scan 00 Sample/Preload Boundary Scan 01 or 10 Bypass Bypass 11 ______________________________________
Table B lists an expanded set of standardized JTAG instructions described by the specification. The additional instructions beyond those included in Table A are described in the JTAG specification in order to standardize the instructions operation.
TABLE B ______________________________________ Full standard JTAG instruction set. PRIOR ART Instruction Name Register IR Code ______________________________________ Extest Boundary Scan 0000 Sample/Preload Boundary Scan 0001 Intest Boundary Scan 0010 Bypass Bypass 1111 Clamp Bypass 0011 HighZ Bypass 0100 Idcode Device ID 0101 Usercode Device ID 0110 Runbist Test Data 0111 or Boundary Scan ______________________________________
FIG. 4 lists an example flow diagram of the operation sequences required to transition between standardized instructions. FIG. 4 lists a typical operation sequence for an IDCODE instruction followed by a SAMPLE/PRELOAD instruction. This particular sequence is commonly performed upon initial power-up of a circuit board that has been designed to use the JTAG interface for board testing.
In FIG. 4, the IDCODE instruction is first executed to ensure that the proper devices are in place on the board. In step 411, the devices identifying codes are shifted out on their TDO pins. The controlling test system compares these code values against the set of expected values. If all of the values match, then all devices are known to be in place, and the JTAG serial data chain is known to be operating correctly. The SAMPLE/PRELOAD instruction may then be used to determine whether the device's OCSL has powered up correctly, and to load data for subsequent test operation. In FIG. 4, step 421, the devices capture initial values presented to their boundary scan register (BSR) cells. In step 422, this initial capture data is shifted out for inspection. At the same time, PRELOAD data is typically shifted into the device's BSR's in preparation for a subsequent EXTEST, INTEST or RUNBIST instruction. Alternatively, steps 406 through 408 may be omitted, since the JTAG specification requires that the IDCODE instruction be loaded into the instruction register whenever a device's TAP controller is in the Test-Logic-Reset state.
In many cases of sequential JTAG instruction execution, there is no dependence between the operations. For example, in FIG. 4, the SAMPLE/PRELOAD operation is in no way dependent upon selection or execution of the previous IDCODE operation. The exceptions to this instruction independence are the execution of a SAMPLE/PRELOAD instruction followed by an EXTEST or INTEST instruction. In these cases, the PRELOAD portion of the SAMPLE/PRELOAD instruction loads data into the BSR. The following EXTEST OR INTEST operation relies on this BSR data to perform a test of either the board level interconnect or of the OCSL operation. However, even in these cases, the OCSL's operation is specifically not altered by the initial SAMPLE/PRELOAD operation. The SAMPLE/PRELOAD instruction serves only to initialize the BSR data for use by the subsequent EXTEST or INTEST instruction. This instruction dependence also applies to a SAMPLE/PRELOAD instruction preceding or following a RUNBIST instruction, if the RUNBIST instruction is designed to utilize the BSR.
It is an object of the invention to extend the functionality and flexibility of the JTAG test logic structure and methodology by defining and including instructions that operate in sequence, such that one instruction is designed and intended to be executed in sequence after one or more preceding instructions, where the preceding instructions modify the operation of the OCSL. It is another object of the invention to devise a methodology by which the OCSL operating mode of the device may be changed by use of state machine and Instruction Register control, with instructions that provide alternate methods for terminating or altering operation initiated by previously executed instructions.